High performance, multi-processor systems with a large number of microprocessors are built by interconnecting a number of node structures, each node containing a small number of microprocessors. This necessitates an interconnection network which is efficient in carrying control information and data between the nodes of the multi-processor.
In the past, crossbar switches, which route communications between the "nodes" of a network, included logic for determining a desired destination from message header, and for appropriately routing all of the parallel bits of a transmission; e.g., 64 bits in parallel for a 64 bit microprocessor. A configuration such as this presents inherent scalability problems, principally because its number of nodes or ports limits each crossbar switch. For example, a typical crossbar switch might service four nodes in parallel, and route 64 bits to one of the four nodes; if more nodes were desired, multiple crossbar switches would be cascaded to support the additional nodes. Such a configuration is not readily scalable either in terms of bandwidth; i.e., such a system could not readily be reconfigured to handle 128 bits in parallel to support higher-performance systems, or because the more cascaded structures, the greater the routing overhead and associated latency. Further, it is difficult to achieve high availability or redundancy with such a configuration.
Thus, a method or architecture has been long sought and long eluded those skilled in the art, which would be scalable and re-configurable while having low latency and high redundancy. The system would be packet switched and provide a high availability (HA) crossbar switch architecture.